The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a vertical transistor and a method for fabricating the same.
In a sub-60 nm DRAM process, formation of vertical transistors is desired in order to increase integration density of transistors in memory cells, to simplify a fabrication process, and to improve device characteristics. A vertical transistor includes an active pillar and a vertical gate surrounding the active pillar. Due to the vertical gate, a channel of a transistor is formed vertically.
Generally, an active pillar has a neck pillar and a top pillar, and a gate surrounds the neck pillar. However, the supporting force of the neck pillar is so weak that the active pillar may collapse in a subsequent process. To solve the limitations of the neck pillar structure, a method of forming a neck-free active pillar has been proposed.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device with a vertical transistor. Referring to FIG. 1A, neck-free active pillars 12 are formed by etching a substrate 11 using a pad layer 13 as an etch barrier. The pad layer 13 is a layer where a pad oxide layer 13A and a pad nitride layer 13B are stacked. A channel region 12A and a drain region 12B are defined in the active pillar 12.
A buried bit line (BBL) 14 is formed by implanting impurity ions into the substrate 11 between the active pillars 12.
A gate dielectric layer 15 is formed, and a gate conductive layer 16 is formed over the gate dielectric layer 15 along a profile of a resulting structure.
Referring to FIG. 1B, the gate conductive layer 16 is etched back to form a vertical gate 16A surrounding the channel region 12A of the active pillar 12.
The gate conductive layer 16 has only to be deposited to a certain thickness, without fully filling the interval (e.g., space in-between) between the active pillars 12. Thus, the vertical gate 16A may be easily formed.
Since the pad nitride layer 13B formed over the active pillar 12 is used as a barrier when an etch process and a chemical mechanical polishing (CMP) process are performed several times, the pad nitride layer 13B needs to have a height of 1,500 Å or more for a subsequent process.
However, since the height of the active pillar is relatively high, it is difficult to remove the gate conductive layer 16 surrounding regions outside the channel region 12A (see a reference symbol “A”). Even though the gate conductive layer 16 is removed, the pad nitride layer 13B may be greatly damaged in a subsequent process (see a reference symbol “B”). As a result, a stable structure may not be obtained.
Moreover, as the semiconductor device shrinks even smaller in size, an aspect ratio of the active pillar to be formed increases and thus it is also difficult to form a stable active pillar.
Meanwhile, resistance of the buried bit line 14 is relatively extremely high because ion implantation is applied for forming the buried bit line 14 in the semiconductor device with the vertical transistor.
To overcome these limitations, silicide or a metal layer is formed over the buried bit line 14.
However, since the active pillar is relatively too high, it is difficult to apply a gap-fill of a metal layer for forming silicide due to a high aspect ratio. It is more likely to cause a bridge between the active pillars in a process of stripping the metal layer.